1. Field of the Invention
The present invention relates to an output stage of a switch mode power supply, in which a pulse width modulator generates a modulated pulse for delivery to an output switching stage via a driver stage. One or more feedback paths provide signals representative of the output of the output stage to an input of the pulse width modulator.
2. Description of the Related Art
With reference to FIG. 1 there is illustrated a typical prior art structure of a switch mode power supply including a pulse width modulator (PWM) generator.
As illustrated in FIG. 1, there is provided a PWM generator 10, a driver stage 12, and an output stage 14 in the switch mode power supply.
The PWM generator 10 generates pulse width modulated signals on a first output 26 and optionally on a second output 28, the signals on the second output being the inverse of the signals on the first output. The PWM generator 10 generates the pulse width modulated signals at its output(s) in dependence on a reference input signal REF on line 9.
The driver stage 12 receives the pulse width modulated signals on lines 26 (and optionally on line 28), and generates corresponding drive signals on line 30 and line 32. The drive signals on line 30 and on line 32 are provided as inputs to the output stage 14.
In the illustrated example of FIG. 1, the output stage includes a half-bridge arrangement comprising a pair of push-pull transistors, illustrated as FETs 16 and 18. The high-side FET 16 has its channel connected between a supply voltage VDD and an output node, and the low-side FET 18 has its channel connected between the output node and electrical ground. The control nodes of the FETs 16 and 18 are respectively connected to receive the drive signals on lines 30 and 32.
The output stage 14 may be one stage of n output stages, each output stage providing one of n phases of an n-phase converter.
The output node provides an output signal on line 34, which is delivered to a filter 20 before the output signal OUT is generated on line 36. The filter 20 comprises an inductor connected between the lines 34 and 36, and a capacitor 24 connected between the line 36 and electrical ground.
The closed loop operation of the switch mode power supply of FIG. 1 is provided by a feedback loop from the output of the output stage 14 to the input of the PWM generator 10. This feedback may be an output current feedback or an output voltage feedback, or both. In FIG. 1 a connection line 33 represents an output voltage feedback, providing the output voltage on line 36 to an input of the PWM generator 10. Also shown in FIG. 1 is a connection line 35 representing an output current feedback, providing the output current on line to an input of the PWM generator 10. The provision of voltage and current feedback loops, and their implementation to provide a feedback, is well-known in the art. As is also well-known in the art, the PWM generator 10 is adapted to generate the PWM output signals in dependence on the reference signal on line 9 modified by the feedback signals on lines 33 or 35.
As can be understood with reference to FIG. 1, to drive the transistors of the output stage 14 the driver stage 12 is required to be capable of generating signals for both the high-side (FET 16) and the low-side (FET 18) output switching transistors. In certain applications it is advantageous for the transistors of the output stage 14 to have a high switching speed. However the limitations of commercially available integrated circuit drivers for the driver stage 12 are such that they can introduce a significant delay (typically, with current technologies, of the order of 70 to 150 ns). This problem is particularly acute for high voltage drivers, e.g. of the order of 50V and greater. Moreover the delay affects the performance of the closed loop operation as it limits the maximum stable closed loop bandwidth. The delays also mean that the fast switching speeds of an output switching stage constructed with fast transistors, such as GaN transistors, cannot be fully exploited.
It is an aim of the present invention to provide an improved output stage for use in a high bandwidth closed loop application, which enables the potential switching speed of the output stage to be realised, and/or which improves the closed loop bandwidth.